Integrated Course in ASIC Verification

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Integrated Course in ASIC Verification

Integrated Course in ASIC Verification is a comprehensive training program on ASIC Design and Verification, with the course syllabus extending from basics of Digital Electronics and Verification concepts, all the way up to building complex Verification environments using UVM. An all-inclusive one-stop solution to transform you into a Professional VLSI Design and Verification Engineer of current day industry standards.

 

Integrated ASIC Verification Course Content:

Integrated Course in ASIC Verification Training is a combination of

Final Project

  • Build a Constrained Random Coverage Driven testbench using SystemVerilog for a complex design
  • Build a UVM Testbench for a complex design

Assignments & Labs:

  • Building Verification Environments in Verilog
  • Building a Constrained Random SystemVerilog testbench
  • Building an Advanced UVM testbench
  • Functional Coverage and RAL Integration
  • Final Project

Prerequisites:

  • BE or ME in Electrical Engineering, Computer Engineering, VLSI or Equivalent
  • High Quality Internet Connection

EDA Tools:

  • QuestaSim Functional Verification tool from Mentor Graphics