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Design Verification Services
VeriFast Technologies
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The Leader in VLSI Design Verification Services
Achieve The Coverage Results You Need With a Faster Time-to-Market Partner Approach

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Integrated ASIC Verification Course Content

Integrated Course in ASIC Verification Training is a combination of

JumpStart: ASIC Verification
BootCamp: SystemVerilog
BootCamp: UVM

Final Project

Build a Constrained Random Coverage Driven testbench using SystemVerilog for a complex design
Build a UVM Testbench for a complex design

Register now to start learning
ASIC Verification in the cloud… instantly!

UVM (Universal Verification Methodology) Training Content

UVM Overview

UVM Evolution
UVM Structural Pieces and Classes
Phases, Reporting, Factory and Config_db
Introduction to Register Abstraction Layer (RAL)

Writing a Simple UVM Testbench

UVM Classes and Field Macros
UVM Environment Architecture
TB Top, Test, Environment, Agent
Sequencer, Driver, Monitor, Scoreboard
Sequence and Sequence Item
Factory Overriding

Functional Coverage Integration

Signal level Functional Coverage
Transaction level Functional Coverage
Integrating Functional Coverage into UVM Testbench

UVC integration

UVM Verification Component (UVC)
UVC Integration into Environment

Writing an advanced UVM Testbench I

Custom register model building
Virtual Sequence and Virtual Sequencer

RAL Concepts

RAL introduction
Register block
Adapter and predictot
Register Access Methods
RAL sequences

Writing an advanced UVM Testbench II

Interrupt Handling
RAL integration into UVM Testbench
RAL methods usage in UVM testbench

Final Project

Build a UVM Testbench for a complex design

Register now to start learning
ASIC Verification in the cloud… instantly!

ASIC Verification Training Course Content

Digital Design Fundamentals

Basic Fundamentals (Number System, Boolean Algebra, Logic Gates, Logic Optimizations)
Combinational Logic Design
Sequential Logic Circuits & Finite State Machines

Verilog For Design

Concept & Fundamentals
Structural Modeling
Behavioral Modeling
Building Behavioral Models

Verilog For Verification

Verilog Operators & Directives
Verilog Testbench Constructs
Built-in System Functions & Tasks
File I/O Operations
Randomization & Control Functions

Verification Architecture

Verification Flow and Simulation Process
Types of Testbench – Architecture and Applications
Testbench Building Blocks
Verification Architecture

Scripting & Automation

Shell scripts & Linux commands
Perl Scripts
Makefile

Writing Testbench : Verilog (Hands-on Lab)

Testbench Architecture
Testbench Building blocks
Step-by-step Guidelines

Final Project

Build Verification IP for one or more the standard based interface like I2C, SPI, AHB and UART.

Register now to start learning
ASIC Verification in the cloud… instantly!

SystemVerilog Training Content

SystemVerilog Fundamentals

SV Introduction
Data Types
Operations and Expressions
Procedural Statements and Control Flow

SystemVerilog Extended features

Inter-process Communication
Interface
Program Blocks

OOP Concepts

OOP Concepts
Classes
Randomization and Constraints

Verification Architecture

SV Testbench Architectures
Verification Flow and Simulation Process
Types of Testbench – Architecture and Applications
Testbench Building Blocks
Verification Architecture

Writing a Testbench in System Verilog

Virtual interface
TB Top
Generator, Driver, Monitor
Scoreboard, Config and Package

Functional Coverage and DPI

Functional Coverage
DPI

Functional coverage integration

Signal and Transaction level Functional Coverage
Integrating Functional Coverage into SV Testbench

Functional coverage integration

Build a Constrained Random Coverage Driven testbench using SystemVerilog for a complex design

Register now to start learning
ASIC Verification in the cloud… instantly!

SystemVerilog & UVM Training Content

System Verilog Fundamentals

SV Introduction
Data Types
Operations and Expressions
Procedural Statements and Control Flow

SystemVerilog Extended features

Inter-process Communication
Interface
Program Blocks

OOP Concepts

OOP Concepts
Classes
Randomization and Constraints

Verification Architecture

Verification Flow and Simulation Process
Types of Testbench – Architecture and Applications
Testbench Building Blocks
Verification Architecture

Writing a Testbench in System Verilog

Virtual interface
TB Top
Generator, Driver, Monitor
Scoreboard, Config and Package
Environment and Test

Introduction to UVM

UVM Advantages
Typical UVM testbench
Class hierarchy
Phases

Final Project

Build a Verification environment using SystemVerilog for a simple design: UART.

Register now to start learning
ASIC Verification in the cloud… instantly!