Founded in 2012, VeriFast Technologies is the leader in ASIC Verification Training and Consulting.

Our training programs are designed for entry-level to seasoned engineers, and they are great for individuals and teams.

Our training programs and consulting expertise is in ASIC Verification with an intense focus on SystemVerilog and UVM.

Our clients range from semiconductor giants to startups.

Mike Chandler

(CEO and Co-founder)

Mr. Chandler has more than 15 years of marketing and selling design services and EDA tools to the semiconductor and technology sectors where he has been responsible for generating more than $50M in revenue. He earned his Bachelor’s Degree in Strategic Management from California State University, Sacramento. In addition to his role as CEO at VeriFast, Mr. Chandler is also President and CEO of ASICSoft, one of VeriFast’s technology partners. Mr. Chandler is responsible for overall company vision, forging key technology partnerships, and directing the sales and marketing effort for VeriFast.

Shashank Bharadwaj

(General Manager India Operations)

Shashank Bharadwaj brings more than 18 years of experience in the Semiconductor industry with expertise in ASIC Design & Verification and state of the art DSP based SW product development. Prior to joining VeriFast Technologies, Shashank has played leadership and engineering roles in Broadcom & Tektronix. He has been instrumental in leading cross functional teams across geographies to ensure timely delivery of quality products and to consistently meet client expectations.
Shashank has an MS from University of South Florida, majoring in Semiconductor/VLSI. After a stint in the US in Florida and the Silicon Valley, Shashank is currently based in Ahmedabad, India.

Montukumar Makadia

(Strategic Business Advisor)

Montu Makadia has more than 27 years of rich experience, in Sales and Business Development, working very closely with Top Level EDA, Semiconductor and Embedded System Companies. He has been instrumental in setting up successful businesses for both products and services companies targeting Chip Design, Verification and Embedded Firmware development. He has held leading director level roles at EVE Design Automation, Synopsys, and eInfochips. He completed his Bachelors’ degree in Electronics and Communication Engineering from Manipal Institute of Technology in 1993 and holds a post graduate diploma in VLSI Design.

Mike Chandler

Shashank Bharadwaj

Montukumar Makadia

Integrated ASIC Verification Course Content

Integrated Course in ASIC Verification Training is a combination of

Final Project

UVM (Universal Verification Methodology) Training Content

UVM Overview

Writing a Simple UVM Testbench

Functional Coverage Integration

UVC integration

Writing an advanced UVM Testbench I

RAL Concepts

Writing an advanced UVM Testbench II

Final Project

ASIC Verification Training Course Content

Digital Design Fundamentals

Verilog For Design

Verilog For Verification

Verification Architecture

Scripting & Automation

Writing Testbench : Verilog (Hands-on Lab)

Final Project

SystemVerilog Training Content

SystemVerilog Fundamentals

SystemVerilog Extended features

OOP Concepts

Verification Architecture

Writing a Testbench in System Verilog

Functional Coverage and DPI

Functional coverage integration

Functional coverage integration

SystemVerilog & UVM Training Content

System Verilog Fundamentals

SystemVerilog Extended features

OOP Concepts

Verification Architecture

Writing a Testbench in System Verilog

Introduction to UVM

Final Project

About Us

Mike Chandler

Shashank Bharadwaj

Montukumar Makadia