Complexities in the modern age ASIC Designs has driven the need for more advanced functional verification techniques to minimize development risk. Verification IP promote reusability to bring down cost & provide necessary infrastructure for test-bench generation and checking mechanisms, as well as all the appropriate routines to create individual protocols or bus functional models.
VeriFast VIP solutions enable verification engineers to focus on verifying their designs rather than spending an excessive amount of time setting up complex verification environments.
Our Verification IP portfolio includes:
All our Verification IPs are developed in SystemVerilog UVM and will be available soon as a part of vPivotal.com
Verifast offers C1B compression and D8B decompression cores specifically designed for use in enterprise class SSD applications. A critical requirement for enterprise SSDs is to keep read latency at a minimum, while maintaining high bandwidth. To meet that requirement, the D8B decompression core operates at a peak rate of 8 bytes per clock, with latency < 0.5 us. In contrast, compression is in the write path, which is typically not latency sensitive. Hence, C1B is designed for 1 byte per clock and optimized for best compression ratio. Multiple engines can be instantiated in a single design to reach desired performance goals.