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Semiconductor Design Verification is an evolving field with continuous enhancements to the existing Verification Methodologies. Our Experts work tirelessly to create/enhance/update training modules to provide detailed insight into the latest verification methodologies. Utmost attention is given to the latest trends in the world of verification and chip design. Training modules cover the following aspects:
• Verification Architecture
• Test Bench Development
• Test Plan Development
• Test Plan Implementation
• Transaction Level Modeling
• Bus Functional Models
• Code & Functional Coverage
• Verification Sign-off
• System Verilog (UVM, OVM, VMM)
• SystemC, C/C++, Perl, Specman e, Vera
• ASIC, SoC, FPGA (Xilinx & Altera)